In recent years, an organic EL display using organic electroluminescence (EL) has been attracting attention as one of the next-generation flat-panel displays replacing the liquid crystal displays. A thin-film transistor array in which thin-film transistor (TFT) elements are arranged in a matrix is used for an active-matrix display device such as the organic EL display.
A bottom-gate thin film transistor array in which the gate electrodes are formed on a side toward the substrate with respect to the silicon layer is generally used for the thin-film transistor array. FIG. 10 is a perspective view schematically illustrating the laser annealing in a conventional thin-film transistor array manufacturing method. A conventional thin-film transistor array 500 is manufactured as follows (for example, see the patent literatures 1 and 2).
First, a substrate 51 is prepared (first process), and an undercoat layer 52 is formed on the substrate 51. Next, gate electrodes 53a and 53b are formed on the undercoat layer 52 (second process). Subsequently, a gate insulating layer 56 is formed on the gate electrodes 53a and 53b (third process). The gate insulating layer 56 is formed by stacking a silicon nitride film 54 and a silicon oxide film 55. For example, the thickness of the silicon nitride film 54 is approximately 65 nm, and the thickness of the silicon oxide film 55 is approximately 85 nm. Subsequently, an amorphous silicon layer 57 made of amorphous silicon is formed on the gate insulating layer 56 (fourth process). For example, the thickness of the amorphous silicon layer 57 is approximately 45 nm. After that, a crystalline silicon layer 58 made of polysilicon (polycrystalline silicon) is formed by the laser annealing (fifth process). With the laser annealing method, as illustrated in FIG. 10, a laser light source (not illustrated) is moved in a predetermined direction relative to the substrate 51 such that the amorphous silicon layer 57 is entirely irradiated with the laser beam. With this, the amorphous silicon layer 57 is entirely crystallized with the heat generated by the laser beam, thereby forming the crystalline silicon layer 58. Subsequently, in regions above the crystalline silicon layer 58 corresponding to the gate electrodes 53a and 53b, source electrodes (not illustrated) and drain electrodes (not illustrated) are formed (sixth process).